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Cisco 8PTCHANNELIZED T1 E1 TO DS0 SH

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  • Cisco
  • 41133803
  • SPA-8XCHT1/E1-RF
  • Temporarily Out-of-Stock
  • Call for next available delivery
Ordering Information
  • Supports Frame Relay, HDLC, PPP Networking
  • Remote Management over SNMP
Today's global enterprise and service provider networks require diverse networking solutions to meet both economic and evolving connectivity needs. The demand for high-density, cost-effective solutions increases as corporate intranets expand to include more regional offices and increased numbers of remote and mobile users, while maintaining network requirements for scalability and improved price for performance.

The Cisco 8-Port Channelized T1/E1 SPA provides one of the greatest densities currently offered in the industry at 8 ports per SPA and up to 32 ports per SIP. At a cost per T1/E1 port less than that of a standard serial port with external channel service unit/data service unit (CSU/DSU), the Cisco 8-Port Channelized T1/E1 SPA is cost-effective for all WAN connectivity.

The Cisco 8-Port Channelized T1/E1 SPA is designed to provide a full 8-port channelized solution for the Cisco 7600 Series routers. The interfaces can be channelized, fractional, or unframed (E1) with up to 256 independent High-Level Data Link Control (HDLC) channels definable for T1 and E1 applications. With these capabilities, the Cisco 8-Port Channelized T1/E1 SPA eliminates the need for separate interface types for separate connection requirements.

Multilink Point-to-Point Protocol (MLPPP) is supported (in hardware) to enable link aggregation >T1. Up to eight individual T1s can be combined within a multilink bundle that appears to be a single IP link. This enables service providers to provision bandwidth >T1 incrementally, without requiring migration of the circuit and customer premises equipment (CPE) infrastructure to T3 facilities.

The Cisco 8-Port Channelized T1/E1 SPA is hot-swappable and supports service-transparent online insertion and removal (OIR), allowing removal of the SPA without impacting the interface processor and other SPAs.
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